صفحه محصول - پاورپوینت معماري کامپيوتر- درس نهم

پاورپوینت معماري کامپيوتر- درس نهم (pptx) 29 اسلاید

دسته بندی : پاورپوینت

نوع فایل : PowerPoint (.pptx) ( قابل ویرایش و آماده پرینت )

تعداد اسلاید: 29 اسلاید

قسمتی از متن PowerPoint (.pptx) :

معماري کامپيوتر- درس نهمpipeline برگرفته از درس : Prof. David A. Patterson Pipelining: Its Natural! Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes “Folder” takes 20 minutes Sequential Laundry Sequential laundry takes 6 hours for 4 loads If they learned pipelining, how long would laundry take? 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time Pipelined Laundry Pipelined laundry takes 3.5 hours for 4 loads 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time Pipelining Lessons Pipelining doesn’t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to “fill” pipeline and time to “drain” it reduces speedup 6 PM 7 8 9 T a s k O r d e r Time Computer Pipelines Execute billions of instructions, so throughput is what matters What is desirable in instruction sets for pipelining? Variable length instructions vs. all instructions same length? Memory operands part of any operation vs. memory operands only in loads or stores? Register operand many places in instruction format vs. registers located in same place? A "Typical" RISC 32-bit fixed format instruction (3 formats) Memory access only via load/store instructions 32 32-bit GPR 3-address, reg-reg arithmetic instruction; registers in same place Single address mode for load/store: base + displacement no indirection Simple branch conditions Delayed branch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 5 Steps of MIPS DatapathFigure 3.1, Page 130, CA:AQA 2e Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc L M D MUX Memory Reg File MUX MUX Data Memory MUX Sign Extend Zero? Next SEQ PC Next PC WB Data RD RS1 RS2 Imm 5 Steps of MIPS DatapathFigure 3.4, Page 134 , CA:AQA 2e Memory Access Write Back Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Reg File MUX MUX Data Memory MUX Sign Extend Zero? Next SEQ PC Next SEQ PC RD RD RD WB Data Data stationary control local decode for each instruction phase / pipeline stage Next PC RS1 RS2 Imm MUX